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IEEE SWISS SSCS TALK : 55nm DDC Subthrehold MCU 2.5uA/MHZ by Marc Pons (Senior Engineer CSEM)

June 26, 2019 @ 17:30 - 18:30 CEST

Dear Colleagues,

CSEM stand with a long Experience in ultra-low-power digital implementation.
Since the 80’s, and the pioneer work of CSEM, Technology did not stand still.
 
Today’s FinFet, FDSOI, SOTB offers improved opportunities. This work exploit strong body factor of deeply-depleted channel CMOS at 0.5V to compensate frequency over PVT to ±6%, achieving 30x frequency and 20x leakage scaling in a 2.56uW/MHz RISC-Core with 3.13nW/kB 2.5uW/MHz SRAM. The whole system offer Frequency-leakage configurability implemented by current-controlled adaptive body bias at a fixed supply voltage.
 
The paper presented as of CICC 2019, set a World record for MCU Energy efficiency.
 
We look forward to hear from Marc.

Speaker(s): Marc Pons,

Location:
Room: E81
Bldg: ETZ Building Floor E
ETH Zurich IIS Departement
Gloriastrasse, 35
Zurich, Switzerland
8092

Details

Date:
June 26, 2019
Time:
17:30 - 18:30
Website:
http://events.vtools.ieee.org/m/199587

Venue

Room: E81, Bldg: ETZ Building Floor E